1. Field of the Invention
The present invention generally relates to high speed receiving and latching and, more particularly, to high speed receiving and latching single-ended signals into a self-resetting CMOS (SRCMOS) circuit.
2. Description of the Prior Art
The main memory portion of modem computers often employ arrays of static random access memory (SRAM) cells, each capable of storing one bit of data. When a bit is read out from a cell, it is normally output to a latch circuit to be held for further processing. Each SRAM cell is typically comprised of a flip-flop having two bit lines, one outputting a logic level indicative of the stored bit and the other outputting its complement. Unfortunately, due to non-ideal conditions or simply when bridging from one logic family to another, the output voltage on either of the bit lines is not necessarily a full logic high or low, but rather something in between which is indefinite to a subsequent reading circuit. This indefiniteness necessitates the use of a separate sensing or receiving circuit to read the SRAM cell to determine the correct logic level of the data bit stored in the SRAM cell. Typically, the logic level is resolved by comparing the SRAM cell bit line to its complement bit line. Once the correct logic level is determined, the data bit is clocked into a latch to be held for further processing. After each cycle the receiver and latch must be reset by the clock to make ready for the next input signal.
U.S. Pat. No. 5,239,506 to Dachtera et al. shows a latch and data out driver for reading a SRAM memory cell as discussed in the preceding paragraph. Dachtera et al. employs a sense amplifier which senses and amplifies a voltage differential across complementary bit lines from a memory cell. Dual outputs from the sense amplifier are fed into a latch driving circuit which in turn is connected to the latch where the actual value of the bit stored in the memory cell is held. For certain applications only a single-ended input or bit line is available as in input to the receiver. Since a complementary bit line is not available for comparison purposes the Dachtera et al. device unsuitable.
U.S. Pat. No. 4,614,885 to Brosch et al. shows a traditional static receiver and latch implemented in a bipolar technology which is capable of receiving a single-ended bit line. However, the Brosch device still relies on a comparison between the input and a reference voltage to determine the value of the input bit. Another major drawback to the Brosch et al. receiver is that it is not edge triggered which means that input data must remain stable the entire time that the clock signal is active. Fluctuations in the input signal during this critical time may result in erroneous data being latched.